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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adp3410 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 dual mosfet driver with bootstrapping features all-in-one synchronous buck driver one pwm signal generates both drives anticross-conduction protection circuitry programmable transition delay synchronous override control undervoltage lockout programmable overvoltage shutdown v cc good signal drives auxiliary circuits shutdown quiescent current < 10 a applications mobile computing cpu core power converters multiphase desktop cpu supplies single-supply synchronous buck converters standard-to-synchronous converter adaptations general description the adp3410 is a dual mosfet driver optimized for driving two n-channel fets that are the two switches in the non- isolated synchronous buck power converter topology. each of the drivers is capable of driving a 3000 pf load with a 20 ns propagation delay and a 30 ns transition time. one of the drivers can be bootstrapped, and is designed to handle the high- voltage slew rate associated with ? oating high-side gate drivers. the adp3410 has several protection features: overlapping drive prevention (odp), undervoltage lockout (uvlo) with perform- ance speci ? ed at very low vcc levels, and overvoltage protection (ovp) that can be used to monitor either the input or output. additional features include: programmable transition delay, a synchronous drive override control pin, a synchronous drive status monitor and, in conjunction with exiting from the uvlo mode, a v cc good (vccgd) signal capable of driving a 10 ma load. the quiescent current, when the device is disabled, is less than 10 m a. gnd pgnd sd in drvlsd srmon ovpset dly vcc vccgd bst drvh sw drvl adp3410 to pwm controller 5v v batt v out figure 1. typical application circuit functional block diagram v cc v cc control and overlap protection circuit adp3410 4.4v 1.2v vcc vccgd gnd sd in dly ovpset drvlsd pgnd bst drvh sw drvl srmon
rev. a ?2? adp3410especifications 1 parameter symbol conditions min typ max unit supply supply voltage range v cc 4.15 5.0 6.0 v quiescent current i ccq shutdown mode v sd < 0.8 v 10 m a operating mode v sd > 2.0 v, no switching 1 2 ma vccgd output output voltage high v cc = 4.6 v, i load = 10 ma 4.5 4.55 v output voltage low v cc < uvlo, i load = 10 m a 0.1 0.2 v vccgd propagation delay 2, 3 tpdh vccgd , sd s vd sd l srsrr r v v vl v v ld v sr sr v v ld d sr drvlsd drvl drvlsdl sr drvlsd drvll drvll vl v vl v vll v vl d vl v s vl v l vrvlr v v v d v v vvs srsrrl drvlsd v v vl v d drvlsd v v s drvlsd lddrvl sd v v vl v v v vl v rlsd sd
rev. a ?3? adp3410 parameter symbol conditions min typ max unit low-side driver output resistance, sourcing current v cc = 4.6 v 2.5 5 w output resistance, sinking current v cc = 4.6 v 2.5 5 w drvl transition times 2 tr drvl, v cc = 4.6 v, c load = 3 nf 20 35 ns (see figure 6) tf drvl drvl propagation delay 2, 3 tpdh drvl v cc = 4.6 v 5 30 ns (see figure 6) tpdl drvl 25 ns notes 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. 2 ac speci ? cations are guaranteed by characterization, but not production tested. 3 for propagation delays, tpdh refers to the speci ? ed signal going high, tpdl refers to it going low. 4 propagation delay measured until drvl begins its transition. 5 logic inputs meet typical cmos i/o conditions for source/sink current (~1 ma). 6 maximum propagation delay = 40 ns max + (1 ns/pf c dly ). speci ? cations subject to change without notice. absolute maximum ratings * vcc to pgnd . . . . . . . . . . . . . . . . . . . . . . . . ? 0.3 v to +7 v bst to pgnd . . . . . . . . . . . . . . . . . . . . . . . . ? 0.3 v to +30 v bst to sw . . . . . . . . . . . . . . . . . . . . . . . . . . . ? 0.3 v to +7 v sw to pgnd . . . . . . . . . . . . . . . . . . . . . . . . ? 2.0 v to +25 v ovpset to pgnd . . . . . . . . . . . . . . . . . . . . ? 0.3 v to +10 v sd drvlsd d vv dd v r
rev. a adp3410 ?4? pin function descriptions pin mnemonic function 1 ovpset overvoltage shutdown sense input. shutdown occurs when this pin is driven above the speci ? ed thresh- old. it is a high-impedance comparator input, so an ext ernal resistor divider can be used to scale the controlling voltage for ovp. 2 sd svddrvdrvl d sdl l drvlsd sr drvl drvl drvlsd drvl dl ld dl dl vd v v vlvdv v sd drvl sr d d s sr sr drvlsd srdrvl drvlsd srl s v vd drv d s s ss r vs sd d drvlsd dl v d s drv s sr d drvl v v s d
rev. a ?5? adp3410 bias enable v cc vcc 4.4v uvlo delay drvl 10% v cc 1.2v vcc 1v adp3410 c bst vcc 5v d1 drvh sw drvl pgnd srmon bst gnd v batt q1 q2 c dly rb sd vccgd dly in ovpset drvlsd ra v out figure 2. functional block diagram tpdh drvlsd 2.0v 0.8v tpdl drvlsd drvl drvlsd in figure 3. drvlsd d
rev. a adp3410 ?6? 2v 0.8v 3.5v tpdh vccgd tpdi vccgd 10% v cc vccgd sd figure 4. vccgd propagation delay 10% v cc tpdh uvlo tpdi uvlo vccgd v cc uvlo threshold uvlo threshold?hysteresis 90% v cc figure 5. uvlo propagation delay in drvl drvh-sw sw tpdl drvl tf drvl tr drvh tpdh drvh tpdl drvh tf drvh tr drvl v th v th 1v tpdh drvl 90% 10% 90% 10% 90% 10% 10% 90% figure 6. nonoverlap timing diagram
rev. a drvh drvl in v cc = 5v c load = 3nf v sw = 0v voltage time ? ns 20ns/div 2v/div tpc 1. drvh fall and drvl rise times ambient temperature ? c 30 25 0 0 85 25 time ? ns 50 75 20 15 10 5 35 rise time fall time v cc = 5v c load = 3nf tpc 4. drvl rise and fall times vs. temperature junction temperature ? c 30 25 0 0 25 time ? ns 50 75 tpdl drvh v cc = 5v c load = 3nf tpdl drvl 20 15 10 5 100 125 tpc 7. propagation delay vs. temperature drvl drvh in v cc = 5v c load = 3nf c dly = 20pf voltage time ? ns 20ns/div 2v/div tpc 2. drvl fall and drvh rise times capacitance ? nf 40 0 6 1 time ? ns 2345 v cc = 5v t a = 25 c 30 20 10 0 drvh drvl tpc 5. drvh and drvl rise times vs. load capacitance in frequency ? khz 40 0 supply current ? ma 35 20 15 10 5 30 25 0 1200 200 400 600 800 1000 v cc = 5v t a = 25 c c load = 3nf tpc 8. supply current vs. frequency junction temperature ? c 30 25 0 0 85 25 time ? ns 50 75 20 15 10 5 rise time fall time v cc = 5v c load = 3nf tpc 3. drvh rise and fall times vs. temperature capacitance ? nf 35 0 time ? ns 30 25 20 15 10 5 0 123456 v cc = 5v t a = 25 c drvh drvl tpc 6. drvh and drvl fall times vs. load capacitance junction temperature ? c 11.0 10.5 9.0 0 125 25 supply current ? ma 50 75 100 10.0 9.5 v cc = 5v f in = 250khz c load = 3nf tpc 9. supply current vs. temperature t ypical performance characteristicseadp3410 ?7?
rev. a adp3410 ?8? theory of operation the adp3410 is a dual mosfet driver optimized for driving two n-channel fets in a synchronous buck converter topology. a single pwm input signal is all that is required to properly drive the high-side and the low-side fets. each driver is ca pable of driving a 3 nf load with only a 20 ns transition time. a more detailed description of the adp3410 and its features follows. refer to the functional block diagram. low-side driver the low-side driver is designed to drive low-r ds(on) n-channel mosfets. the maximum output resistance for the driver is 5 w s for both sourcing and sinking gate current. the low-output resistance allows the driver to have 20 ns rise and fall times into a 3 nf load. the bias to the low-side driver is internally con- nected to the vcc supply and pgnd. when the driver is enabled, the driver ? s output is 180 drvlsd drvlsd drvlsd drvlsd drvlsd drvl
rev. a ?9? adp3410 synchronous rectiter monitor the synchronous recti ? er monitor provides a ttl output signal for use by the pwm controller. the srmon output follows the drvl signal when the low-side driver is enabled and goes high when the low-side driver is shut down. shutdown the shutdown input is used for power management. if the cir- cuits running off of the buck converter are not needed, the adp3410 can be shut down to conserve power. when the sd d sd vddrv drvl v l vl v vl vvl v v v vd v vlvd s vl vdv s vl sd dvd vd v s d c q v bst gate bst = d (1) where q gate is the total gate charge of the high-side fet, and d v bst is the voltage droop allowed on the high-side fet drive. for example, the irf7811 has a total gate charge of about 20 nc. for an allowed droop of 200 mv, the required bootstrap capacitance is 100 nf. look for a good quality ceramic capacitor. a schottky diode is recommended for the bootstrap diode due to its low forward drop, which maximizes the drive available for the high-side fet. the bootstrap diode must have a minimum 40 v rating to withstand the maximum battery voltage plus 5 v. the average forward current can be estimated by: iqf f avg gate max () a (2) where f max is th e maximum switching frequency of the controller. the peak surge current rating should be checked in circuit since this is dependent on the source impedance of the 5 v supply, and the esr of c bst . setting the ovp threshold the adp3410 can shut down the high-side fet drive when the ovpset input exceeds the threshold voltage. the voltage at which v out trips the overvoltage protection is set by selecting the values for ra and rb shown in figure 2. the threshold for the ovp is calculated using: vv ra rb ovp =+ ? ? ? 12 1 . (3) where v ovp is the desired ovp threshold voltage at v out . in order to minimize the bias current error, rb should be less than or equal to 24 k w . by selecting a value for rb 24 k w and solving for ra gives the following formula: ra v v rb ovp =- ? ? ? 12 1 . (4) note that the minimum the ovp threshold can be is 1.2 v when ra is zero. delay capacitor selection the delay capacitor, c dly , is used to add an additional delay when the low-side fet drive turns off and when the high-side drive starts to turn on. the delay capacitor adds 1 ns/pf of additional time to the 20 ns of ? xed delay. if a delay capacitor is required, a good quality ceramic capacitor with an npo or cog dielectric or a good quality mica capacitor should be used. both types of capacitors are available in the 1p f to 100 pf range and have excellent temperature and leakage characteristics.
rev. a adp3410 ?10? printed circuit board layout considerations use the following general guidelines when designing printed circuit boards: 1. trace out the high-current paths and use short, wide traces to make these connections. 2. split the ground connections. use separate planes for the signal and power grounds, and tie them together at a single point near the adp3410. 3. the vcc bypass capacitor should be located as close as possi ble to vcc and pgnd pins. typical application circuit the circuit in figure 7 shows how the adp3410 can be com- bined with the adp3421 to form a total power conversion solution for a microprocessor. the combination provides the supply voltages for the core processor, the i/o interface, and the clock. vhys adp3421 1 clset 2 lto 3 lti 4 ltb 5 vid4 6 vid3 7 vid2 8 vid1 9 vid0 10 clkdrv 11 clkfb 12 iodrv 13 iofb 14 sd 15 pwrgd 16 uvlo 17 ssl 18 ssc 19 core 20 dacout 21 gnd 22 out 23 vcc 24 ramp 25 reg 26 cs+ 27 cs? 28 u1 r1 51.1k r2 160k 3.3v r10 10k c2 100nf c3 68 f vron q2 2n3906 c14 100 f m1 irf7811 d2 10bq040 ovpset adp3410 sd gnd in drvlsd dly vccgd vcc drvl pgnd srmon sw drvh bst u2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 c20 10 f q1 mjd210 from cpu r11 220 k r12 470 k c22 1nf c21 1.5nf c1 100nf c31 1pf r16 3.3 k c41 1pf c29 100pf r17 75 k r6 7.5 k r5 10 k r18 576 c23 1nf c25 22nf r21, 10 k r19 2 k r15 332 r22 100 k c18 10pf c28 10 f c17 100nf 5v m2 irf7811 r8 2.2 r9 2.2 m3 irf7811 vin l1 1 h d1 10bq040 r cs 5m c32 15nf c10 10 f c15 10 f c16 10 f c4?c6, c11, c12, c26, c27 220 f 7 vcc on core sense v gate vcc cpu io vcc cp u clk vcc cpu core gnd r20 10 figure 7. typical application circuit
rev. a ?11? adp3410 14-lead thin shrink small outline package (tssop) (ru-14) 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.50 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 coplanarity compliant to jedec standards mo-153ab-1 outline dimensions dimensions shown in millimeters (mm). revision history location page data sheet changed from rev. 0 to rev. a. change figures to tpcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 renumbered figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
rev. a ?12? adp3410 c00151?0?5/02(a) printed in u.s.a.

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